Multiple vertical TFT structures for a vertical bit line architecture
US10468459B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 26, 2017 |
| Grant date | Nov 5, 2019 |
| Priority date | — |
| Expiry date | Jan 25, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/823
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods for implementing a memory array comprising vertical bit lines that are connected to different pairs of vertical thin-film transistors (TFTs) are described. A set of vertical TFTs may be formed such that a first TFT and a second TFT are spaced apart by a first separation distance and a third TFT and the second TFT are spaced apart by a second separation distance. The fabrication of the memory array includes forming a layer of conducting material with a thickness that is greater than half of the first separation distance and less than half of the second separation distance and then performing an anisotropic etch to remove portions of the conducting material such that openings in the conducting material are formed between the pairs of vertical TFTs while preventing openings from forming between the vertical TFTs of each pair of vertical TFTs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.