Handle substrate for use in manufacture of semiconductor-on-insulator structure and method of manufacturing thereof
US10475694B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 21, 2017 |
| Grant date | Nov 12, 2019 |
| Priority date | — |
| Expiry date | Jun 26, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76254
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is provided for preparing a high resistivity silicon handle substrate for use in semiconductor-on-insulator structure. The handle substrate is prepared to comprise thermally stable charge carrier traps in the region of the substrate that will be at or near the buried oxide layer (BOX) of the final semiconductor-on-insulator structure. The handle substrate comprising the stable carrier traps is manufactured by hydrogen ions implantation occurring using at least two different energies, followed by a 2-step thermal treatment. The thermally stable defect structures prepared thereby is stable to anneal at temperatures of at least 1180° C. The defect structure comprises 3-dimensional network of nano-cavities interconnected by dislocations. This wafer can be used as a handle wafer for fabricating silicon-on-insulator (SOI) wafers and further fabricating radio frequency (RF) semiconductor devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.