Semiconductor device
US10475739B2 · kind B2 · utility
4Cited by
8References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2017 |
| Grant date | Nov 12, 2019 |
| Priority date | — |
| Expiry date | Dec 13, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/53295
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device is provided. The semiconductor device includes a substrate comprising a lower wire, an etch stop layer on the substrate, an interlayer insulating layer on the etch stop layer, an upper wire disposed in the interlayer insulating layer and separated from the lower wire and a via formed in the interlayer insulating layer and the etch stop layer and connecting the lower wire with the upper wire, wherein the via comprises a first portion in the etch stop layer and a second portion in the interlayer insulating layer, and wherein a sidewall of the first portion of the via increases stepwise.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.