Microelectronics package providing increased memory component density
US10475766B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 29, 2017 |
| Grant date | Nov 12, 2019 |
| Priority date | — |
| Expiry date | Mar 29, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Examples herein include a solid state drive microelectronics package assembly including a substrate and a plurality of microelectronic components coupled to the substrate. The plurality of microelectronic components may be being separated from one another end-to-end by a component gap. The microelectronics package may further include a die package coupled to the substrate, wherein the die package extends across the component gap and is vertically disposed between the plurality of microelectronic components and the substrate. In some examples, the microelectronics components and the die package are each coupled to the substrate by a plurality of connection components (e.g. a solder ball array). The plurality of connection components may be arranged on the microelectronics components to define one or more open areas devoid of any connection components. The die package may be positioned/nested within the one or more open areas to increase overall microelectronic component density of the microelectronics package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.