Power transistor device
US10475792B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 11, 2018 |
| Grant date | Nov 12, 2019 |
| Priority date | — |
| Expiry date | Oct 11, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
Abstract
Provided is a power transistor device including a substrate structure, a first conductive layer, a second conductive layer and a third conductive layer. The substrate structure has a base portion and fin portions. The fin portions protrude from a surface of the base portion and extend along a first direction. The first conductive layer is disposed across the fin portions and extends along a second direction different from the first direction. The second conductive layer is disposed across the fin portions, is located at one side of the first conductive layer and extends along the second direction. The first spacer is disposed between and in physical contact with the first conductive layer and the second conductive layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.