Method of forming transistor with dual spacer
US10475903B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 28, 2019 |
| Grant date | Nov 12, 2019 |
| Priority date | — |
| Expiry date | Jan 28, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/115
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A transistor with dual spacers includes a gate, a first dual spacer and a second inner spacer. The gate is disposed on a substrate, wherein the gate includes a gate dielectric layer and a gate electrode, and the gate dielectric layer protrudes from the gate electrode and covers the substrate. The first dual spacer is disposed on the gate dielectric layer beside the gate, wherein the first dual spacer includes a first inner spacer and a first outer spacer. The second inner spacer having an L-shaped profile is disposed on the gate dielectric layer beside the first dual spacer. The present invention also provides a method of forming said transistor with dual spacers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.