Gate arrangements in quantum dot devices

US10475912B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Nicole K. Thomas · Portland, US
• Ravi Pillarisetty · Portland, US
• Kanwaljit Singh · Rotterdam, NL
• Hubert C. George · Portland, US
• Jeanette M. Roberts · North Plains, US
• David J. Michalak · Portland, US
• Roman Caudillo · Portland, US
• Zachary R. Yoscovits · Beaverton, US
• Lester Lampert · Portland, US
• James S. Clarke · Portland, US
• Willy Rachmady · Beaverton, US

Key dates

• Filing date: Feb 20, 2018
• Grant date: Nov 12, 2019
• Expiry date: Feb 20, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10N60/80
• WIPO field: Micro-structural and nano-technology
• WIPO sector: Chemistry

Abstract

Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a layer of gate dielectric above the quantum well stack; a first gate metal and a second gate metal above the layer of gate dielectric; and a gate wall between the first gate metal and the second gate metal, wherein the gate wall is above the layer of gate dielectric, and the gate wall includes a first dielectric material and a second dielectric material different from the first dielectric material.