Willy Rachmady
361Patents
18h-index
158Co-inventors
85Inventor score
Filing activity: Jun 30, 2005 → Jan 22, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8753942B2 | Silicon and silicon germanium nanowire structures | Electricity | 131 | Active |
| US7494858B2 | Transistor with improved tip profile and method of manufacture thereof | Electricity | 92 | Expired |
| US9129829B2 | Silicon and silicon germanium nanowire structures | Electricity | 58 | Active |
| US9123567B2 | CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architecture | Electricity | 57 | Active |
| US8987794B2 | Non-planar gate all-around device and method of fabrication thereof | Electricity | 54 | Active |
| US8901537B2 | Transistors with high concentration of boron doped germanium | Electricity | 47 | Active |
| US7838373B2 | Replacement spacers for MOSFET fringe capacitance reduction and processes of making same | Electricity | 44 | Active |
| US7851790B2 | Isolated Germanium nanowire on Silicon fin | Electricity | 37 | Active |
| US8283653B2 | Non-planar germanium quantum well devices | Electricity | 36 | Active |
| US8765563B2 | Trench confined epitaxially grown device layer(s) | Electricity | 34 | Active |
| US9484447B2 | Integration methods to fabricate internal spacers for nanowire devices | Performing Operations; Transporting | 30 | Active |
| US7875519B2 | Metal gate structure and method of manufacturing same | Electricity | 30 | Active |
| US7821044B2 | Transistor with improved tip profile and method of manufacture thereof | Electricity | 30 | Active |
| US8748940B1 | Semiconductor devices with germanium-rich active layers and doped transition layers | Emerging Cross-Sectional Technologies | 28 | Active |
| US7435683B2 | Apparatus and method for selectively recessing spacers on multi-gate devices | Emerging Cross-Sectional Technologies | 20 | Active |
| US8575596B2 | Non-planar germanium quantum well devices | Electricity | 20 | Active |
| US9123790B2 | Contact techniques and configurations for reducing parasitic resistance in nanowire transistors | Emerging Cross-Sectional Technologies | 20 | Active |
| US8441074B2 | Substrate fins with different heights | Electricity | 20 | Active |
| US8193641B2 | Recessed workfunction metal in CMOS transistor gates | Electricity | 18 | Active |
| US9252275B2 | Non-planar gate all-around device and method of fabrication thereof | Electricity | 18 | Active |
| US7560358B1 | Method of preparing active silicon regions for CMOS or other devices | Electricity | 17 | Active |
| US8575653B2 | Non-planar quantum well device having interfacial layer and method of forming same | Electricity | 17 | Active |
| US8264048B2 | Multi-gate device having a T-shaped gate structure | Electricity | 17 | Active |
| US7915642B2 | Apparatus and methods for forming a modulation doped non-planar transistor | Electricity | 14 | Active |
| US9590089B2 | Variable gate width for gate all-around transistors | Emerging Cross-Sectional Technologies | 14 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.