Dual eclipse circuit for reduced image sensor shading
US10477126B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 5, 2018 |
| Grant date | Nov 12, 2019 |
| Priority date | — |
| Expiry date | Sep 5, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/61
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A pixel cell and readout circuit includes an anti-eclipse voltage clamp circuit at both the top and bottom of each column line of an array of the pixel cells. The anti-eclipse voltage clamp circuits form a row with each column in the array coupled to an anti-eclipse voltage clamp circuit. The combination of two rows of anti-eclipse voltage clamp circuits helps settle the clamp voltage more rapidly and to compensate for the increased length of the anti-eclipse voltage circuit row as well as the column line resistance due to narrow metal lines and increased numbers of pixels as well as the requirement to operate a sensor at a higher frame rate. More significantly this circuit construction can minimize vertical shading in the resulting image.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.