Autonomous hardware for application power usage optimization
US10481674B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 20, 2016 |
| Grant date | Nov 19, 2019 |
| Priority date | — |
| Expiry date | Sep 21, 2036 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Self-configured, power-aware circuitry configured to enhance power efficiency within integrated circuitry by self-calibrating the power consumption utilized within the integrated circuitry according to the requirements of an application program running within the integrated circuitry. The power consumption is self-calibrated within the integrated circuitry on a per application-based manner so that the integrated circuitry can be implemented with a plurality of various generalized functionalities, each of which may or may not be utilized while a specific application program is running within the integrated circuitry. Power consumption within the integrated circuitry is reduced by independently and dynamically controlling multiple power sections delineated within the integrated circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.