Jayanta Bhadra
15Patents
3h-index
29Co-inventors
56Inventor score
Filing activity: Feb 13, 2001 → Mar 21, 2018
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6952812B2 | Design analysis tool for path extraction and false path identification and method thereof | Physics | 21 | Expired |
| US9824243B2 | Model-based runtime detection of insecure behavior for system on chip with security requirements | Physics | 5 | Active |
| US9002694B2 | Verification of design derived from power intent | Physics | 4 | Active |
| US8050904B2 | System and method for circuit symbolic timing analysis of circuit designs | Physics | 3 | Active |
| US7945418B2 | Stream based stimulus definition and delivery via interworking | Physics | 2 | Active |
| US10495691B2 | System architecture method and apparatus for adaptive hardware fault detection with hardware metrics subsystem | Physics | 1 | Active |
| US7650579B2 | Model correspondence method and device | Physics | 1 | Active |
| US8555226B1 | Automatic verification of dependency | Physics | 1 | Active |
| US7360183B2 | Design analysis tool and method for deriving correspondence between storage elements of two memory models | Physics | 1 | Expired |
| US8584063B1 | Assertion-based design partitioning | Physics | 1 | Active |
| US9092567B2 | Systems and methods for analyzing transactions in a computer system | Physics | 0 | Active |
| US10481674B2 | Autonomous hardware for application power usage optimization | Emerging Cross-Sectional Technologies | 0 | Active |
| US9069762B2 | Equivalence classes over parameter state space | Physics | 0 | Active |
| US11017077B2 | Run-time security protection system and method | Physics | 0 | Active |
| US8234618B2 | Trace reconstruction for silicon validation of asynchronous systems-on-chip | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.