Circuit to perform dual input value absolute value and sum operation
US10481870B2 · kind B2 · utility
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12References
16Claims
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Key dates
| Filing date | May 12, 2017 |
| Grant date | Nov 19, 2019 |
| Priority date | — |
| Expiry date | May 12, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C19/38
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An execution unit is described. The execution unit includes an arithmetic logic unit (ALU) circuit having a first input to receive a first value and a second input to receive a second value. The ALU circuit includes circuitry to determine an absolute value of the first value and to add the absolute value to the second value. The first input is coupled to a first data path having register space and an output of another ALU of the execution unit circuit as alternative sources of the first value. The second input is coupled to a second data path having the register space as a source for the second value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.