Albert Meixner
73Patents
7h-index
43Co-inventors
64Inventor score
Filing activity: Dec 13, 2012 → Feb 11, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9355483B2 | Variable fragment shading with surface recasting | Physics | 133 | Active |
| US9772852B2 | Energy efficient processor core architecture for image processor | Electricity | 10 | Active |
| US10546211B2 | Convolutional neural network on programmable two dimensional image processor | Physics | 10 | Active |
| US9756268B2 | Line buffer unit for image processor | Electricity | 8 | Active |
| US10915773B2 | Statistics operations on two dimensional image processor | Physics | 8 | Active |
| US9749548B2 | Virtual linebuffers for image signal processors | Physics | 8 | Active |
| US9769356B2 | Two dimensional shift array for image processor | Physics | 7 | Active |
| US10321077B2 | Line buffer unit for image processor | Electricity | 6 | Active |
| US10277833B2 | Virtual linebuffers for image signal processors | Physics | 6 | Active |
| US9986187B2 | Block operations for an image processor having a two-dimensional execution lane array and a two-dimensional shift register | Physics | 4 | Active |
| US10334194B2 | Block operations for an image processor having a two-dimensional execution lane array and a two-dimensional shift register | Physics | 4 | Active |
| US10185560B2 | Multi-functional execution lane for image processor | Physics | 3 | Active |
| US10204396B2 | Compiler managed memory for image processor | Physics | 3 | Active |
| US9965824B2 | Architecture for high performance, power efficient, programmable image processing | Emerging Cross-Sectional Technologies | 3 | Active |
| US10291813B2 | Sheet generator for image processor | Physics | 2 | Active |
| US9224227B2 | Tile shader for screen space, a method of rendering and a graphics processing unit employing the tile shader | Physics | 2 | Active |
| US10095492B2 | Compiler for translating between a virtual image processor instruction set architecture (ISA) and target hardware having a two-dimensional shift array structure | Physics | 2 | Active |
| US10387989B2 | Compiler techniques for mapping program code to a high performance, power efficient, programmable image processing hardware platform | Physics | 2 | Active |
| US10516833B2 | Virtual linebuffers for image signal processors | Physics | 2 | Active |
| US10915319B2 | Two dimensional masked shift instruction | Electricity | 2 | Active |
| US9286114B2 | System and method for launching data parallel and task parallel application threads and graphics processing unit incorporating the same | Physics | 2 | Active |
| US9785423B2 | Compiler for translating between a virtual image processor instruction set architecture (ISA) and target hardware having a two-dimensional shift array structure | Physics | 2 | Active |
| US9978116B2 | Core processes for block operations on an image processor having a two-dimensional execution lane array and a two-dimensional shift register | Physics | 2 | Active |
| US10599407B2 | Compiler for translating between a virtual image processor instruction set architecture (ISA) and target hardware having a two-dimensional shift array structure | Physics | 2 | Active |
| US9830150B2 | Multi-functional execution lane for image processor | Physics | 2 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.