Error detection code hold pattern synchronization
US10482921B2 · kind B2 · utility
6Cited by
1References
20Claims
0Family size
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Key dates
| Filing date | Jan 30, 2019 |
| Grant date | Nov 19, 2019 |
| Priority date | — |
| Expiry date | Jan 30, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1204
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system includes a memory device, a command clock (CK_t clock) that provides a first clock signal at a first frequency, and a data path clock (WCK_t clock) that provides a second clock signal at a second frequency different than the first frequency. Data path circuitry is synchronized with the WCK_t clock and provides an error detection code (EDC) hold pattern during an idle state. EDC hold pattern synchronization logic synchronizes a start of transmission of the EDC hold pattern synchronous to the CK_t clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.