Operation of a memory device during programming
US10482974B1 · kind B1 · utility
2Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 21, 2018 |
| Grant date | Nov 19, 2019 |
| Priority date | — |
| Expiry date | Aug 21, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3427
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods include applying a first voltage level to first and second data lines while applying a second, lower, voltage level to first and second select gates connected between the data lines and respective strings of memory cells; decreasing a voltage level of the first data line to a third voltage level; increasing a voltage level of the first select gate to a fourth voltage level; applying a fifth voltage level, higher than the first voltage level, to first and second access lines coupled to memory cells of the strings of memory cells; and increasing a voltage level of the first access line to a sixth voltage level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.