Vertically stacked multichip modules
US10483237B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 25, 2017 |
| Grant date | Nov 19, 2019 |
| Priority date | — |
| Expiry date | Nov 12, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/83191
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a general aspect, a circuit assembly apparatus can include first and second semiconductor die, and a substrate. The substrate can include an insulating layer; a first metal layer disposed on a first side of the insulating layer, a first side of the first semiconductor die disposed on and electrically coupled with the first metal layer; a second metal layer disposed on a second side of the insulating layer, the second side of the insulating layer being opposite the first side of the insulating layer, a first side of the second semiconductor die being disposed on and electrically coupled with the second metal layer; and a conductive via disposed through the insulating layer, the conductive via electrically coupling the first metal layer with the second metal layer, the first metal layer, the conductive via and the second metal layer electrically coupling the first semiconductor die with the second semiconductor die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.