Semiconductor memory device and method for manufacturing the same
US10483277B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 20, 2017 |
| Grant date | Nov 19, 2019 |
| Priority date | — |
| Expiry date | Apr 21, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/35
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a semiconductor memory device includes a substrate, interconnect portions, a conductive layer, a stacked body, and columnar portions. At least one portion of the interconnect portions is provided inside the substrate, each of the interconnect portions extends in a first direction along a surface of the substrate, and the interconnect portions are arranged along a second direction crossing the first direction. The conductive layer is provided on the interconnect portions. The stacked body is provided on the conductive layer and includes electrode layers stacked to be separated from each other, and each of the electrode layers extends in the second direction. The columnar portions are provided inside the stacked body, each of the columnar portions includes a semiconductor portion extending in a stacking direction of the electrode layers and a charge storage film provided between the semiconductor portion and the stacked body.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.