Method of manufacturing a semiconductor device
US10483279B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 23, 2015 |
| Grant date | Nov 19, 2019 |
| Priority date | — |
| Expiry date | Mar 3, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02667
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor device, comprising the steps of: forming a gate dielectric layer and a first amorphous channel layer on a substrate; thinning the first amorphous channel layer; etching the first amorphous channel layer and the gate dielectric layer until the substrate is exposed; forming a second amorphous channel layer on the first amorphous channel layer and the substrate; annealing such that the first amorphous channel layer and the second amorphous channel layer are converted into a polycrystalline channel layer; and thinning the polycrystalline channel layer. According to the method of manufacturing semiconductor device of the present invention, the grain size of the polycrystalline thin film is increased by depositing a thick amorphous film and then annealing and thinning it. An additional protective layer is used to avoid etching damage on the sidewalls, effectively reducing the interface state and damage defects of the polycrystalline channel layer, thereby enhancing the reliability of the device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.