Power semiconductor device with optimized field-plate design
US10483356B2 · kind B2 · utility
2Cited by
1References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 27, 2018 |
| Grant date | Nov 19, 2019 |
| Priority date | — |
| Expiry date | Feb 27, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/602
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A power semiconductor device and method for making same are disclosed. The device includes a source bonding pad and a drain bonding pad, a drain metallization structure including a drain field plate connected to the drain bonding pad, and a source metallization structure comprising a source field plate connected to the source bonding pad. At least a portion of at least one of the bonding pads is situated directly over an active area. A dimension of at least one of the field plates varies depending upon the structure adjacent to the field plate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.