Interfacial layer between fin and source/drain region
US10483396B1 · kind B1 · utility
7Cited by
0References
20Claims
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Assignee
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Key dates
| Filing date | Jun 11, 2018 |
| Grant date | Nov 19, 2019 |
| Priority date | — |
| Expiry date | Jun 11, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An embodiment is a semiconductor structure. The semiconductor structure includes a substrate. A fin is on the substrate. The fin includes silicon germanium. An interfacial layer is over the fin. The interfacial layer has a thickness in a range from greater than 0 nm to about 4 nm. A source/drain region is over the interfacial layer. The source/drain region includes silicon germanium.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.