High speed interleaver/deinterleaver device supporting line rate, and method thereof
US10484136B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 6, 2017 |
| Grant date | Nov 19, 2019 |
| Priority date | — |
| Expiry date | Sep 15, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/20
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A deinterleaver device, a method for deinterleaving, an interleaver device, and a method for interleaving are provided. The method for deinterleaving includes: providing a memory and a stream count for a frame; virtually dividing the memory into equal sections, wherein a section count equals the stream count; calculating a write address for a sample of the samples based on a location of the sample in the frame and a correspondence of the location to one of the sections; receiving the sample; and writing the received sample to the write address, wherein the calculating and the write address corresponds to a correct deinterleaving location in one of the sections for the sample.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.