Sri Bhat
7Patents
1h-index
8Co-inventors
40Inventor score
Filing activity: May 29, 2012 → Apr 15, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10168938B2 | LDPC decoder design to significantly increase throughput in ASIC by utilizing pseudo two port memory structure | Electricity | 6 | Active |
| US11316585B2 | Channel bonding in an adaptive coding and modulation mode | Electricity | 1 | Active |
| US10419107B2 | Channel bonding in an adaptive coding and modulation mode | Electricity | 1 | Active |
| US10484136B2 | High speed interleaver/deinterleaver device supporting line rate, and method thereof | Electricity | 1 | Active |
| US10819469B2 | High speed interleaver/deinterleaver device supporting line rate, and method thereof | Electricity | 0 | Active |
| US8929501B2 | Method and apparatus for synchronization of data and error samples in a communications system | Electricity | 0 | Active |
| US11658734B2 | Channel bonding in an adaptive coding and modulation mode | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.