Patent · US Active

Via and skip via structures

US10485111B2 · kind B2 · utility

2Cited by
3References
16Claims
0Family size

Assignee

Inventors

Key dates

Filing dateJul 12, 2017
Grant dateNov 19, 2019
Priority date
Expiry dateJul 27, 2037

Classification

  • Technology area (CPC Y)Emerging Cross-Sectional Technologies
  • CPC primaryY10T29/49165
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

The present disclosure generally relates to semiconductor structures and, more particularly, to via and skip via structures and methods of manufacture. The method includes: forming a first metallization layer with a first capping layer over the first metallization layer; forming a second metallization layer with a second capping layer over the second metallization layer; forming a partial skip via structure to the first metallization layer by removing a portion of the first capping layer and the second capping and depositing conductive material in an opening formed in the second metallization layer; forming a third capping layer over the filled partial skip via and the second capping layer; and forming a remaining portion of a skip via structure in alignment with the partial skip via structure by opening the third capping layer to expose the conductive material of the partial skip via.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.