Cycle accurate and cycle reproducible memory for an FPGA based hardware accelerator
US10488460B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 11, 2016 |
| Grant date | Nov 26, 2019 |
| Priority date | — |
| Expiry date | Jul 24, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/331
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method, system and computer program product are disclosed for using a Field Programmable Gate Array (FPGA) to simulate operations of a device under test (DUT). The DUT includes a device memory having a number of input ports, and the FPGA is associated with a target memory having a second number of input ports, the second number being less than the first number. In one embodiment, a given set of inputs is applied to the device memory at a frequency Fd and in a defined cycle of time, and the given set of inputs is applied to the target memory at a frequency Ft. Ft is greater than Fd and cycle accuracy is maintained between the device memory and the target memory. In an embodiment, a cycle accurate model of the DUT memory is created by separating the DUT memory interface protocol from the target memory storage array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.