Address/command chip synchronized autonomous data chip address sequencer for a distributed buffer memory system
US10489069B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 29, 2017 |
| Grant date | Nov 26, 2019 |
| Priority date | — |
| Expiry date | Feb 3, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/205
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communications links in a memory system. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. In one embodiment, the Host only transmits data over its communications link with the data buffer circuit. In one aspect, the memory control circuit does not send a control signal to the data buffer circuits. In one aspect, the memory control circuit and the data buffer circuits each maintain a separate state machine-driven address pointer or local address sequencer, which contains the same tags in the same sequence. In another aspect, a resynchronization method is disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.