Inventor · Hopewell Junction, NY, US

Susan M. Eickhoff

18Patents

3h-index

15Co-inventors

53Inventor score

Filing activity: Dec 14, 2011 → Mar 5, 2021

Most-cited inventions

Patent	Title	Area	Cited by	Status
US8898504B2	Parallel data communications mechanism having reduced power continuously calibrated lines	Electricity	58	Active
US10698440B2	Reducing latency of memory read operations returning data on a read data path across multiple clock boundaries, to a host implementing a high speed serial interface	Physics	5	Active
US10395698B2	Address/command chip controlled data chip address sequencing for a distributed memory buffer system	Physics	4	Active
US10489069B2	Address/command chip synchronized autonomous data chip address sequencer for a distributed buffer memory system	Physics	1	Active
US11099601B2	Reducing latency of memory read operations returning data on a read data path across multiple clock boundaries, to a host implementing a high speed serial interface	Physics	1	Active
US10534555B2	Host synchronized autonomous data chip address sequencer for a distributed buffer memory system	Physics	0	Active
US11587600B2	Address/command chip controlled data chip address sequencing for a distributed memory buffer system	Physics	0	Active
US10740031B2	Interface scheduler for a distributed memory system	Physics	0	Active
US10393805B2	JTAG support over a broadcast bus in a distributed memory buffer system	Physics	0	Active
US10078461B1	Partial data replay in a distributed memory buffer system	Physics	0	Active
US10747442B2	Host controlled data chip address sequencing for a distributed memory buffer system	Physics	0	Active
US10162773B1	Double data rate (DDR) memory read latency reduction	Physics	0	Active
US11687254B2	Host synchronized autonomous data chip address sequencer for a distributed buffer memory system	Physics	0	Active
US10353606B2	Partial data replay in a distributed memory buffer system	Physics	0	Active
US10976939B2	Address/command chip synchronized autonomous data chip address sequencer for a distributed buffer memory system	Physics	0	Active
US10771068B2	Reducing chip latency at a clock boundary by reference clock phase adjustment	Physics	0	Active
US11379123B2	Address/command chip synchronized autonomous data chip address sequencer for a distributed buffer memory system	Physics	0	Active
US10642535B2	Register access in a distributed memory buffer system	Physics	0	Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.