Patent · US Active

Shift amount correction for multiply-add

US10489115B2 · kind B2 · utility

1Cited by

5References

2Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Son T. Dao · Stuttgart, DE
Silvia M. Mueller · Altdorf, DE

Key dates

Filing date	Dec 17, 2014
Grant date	Nov 26, 2019
Priority date	—
Expiry date	Dec 17, 2034

Classification

Technology area (CPC G)Physics
CPC primaryG06F2207/483
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Methods and apparatuses for performing a floating point multiply-add operation with alignment correction. A processor receives a first operand, a second operand and a third operand, wherein the first, second and third operands each represent a floating point number comprising a significand value and a biased exponent value. A processor determines a shift amount based, at least in part, on the one or more biased exponent values of the first, second or third operand. A processor determines a shift amount correction based, at least in part, on the one or more biased exponent values of the first, second or third operand being equal to zero.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.