Prefetching time allocation
US10489297B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 22, 2017 |
| Grant date | Nov 26, 2019 |
| Priority date | — |
| Expiry date | Feb 26, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An example processor that includes a register, a cache, a processor core, and a programmable logic circuit. The register may store a first prefetch value indicating a first amount of time to prefetch data from a memory prior to an execution of a subsequent instruction that uses the data. The processor core may be coupled to the cache and the register. The processor core may execute a prefetch instruction to access the data from the memory, store a copy of the data in the cache, and execute the subsequent instruction. The programmable logic circuit may be coupled to the processor core. The programmable logic circuit may determine whether the first amount of time is insufficient to prefetch the data for the execution of the subsequent instruction and change the first prefetch value to a second prefetch value when the first amount of time is insufficient.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.