Method and apparatus for injecting fault and analyzing fault tolerance
US10489520B2 · kind B2 · utility
3Cited by
10References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 13, 2016 |
| Grant date | Nov 26, 2019 |
| Priority date | — |
| Expiry date | Sep 9, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2117/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed herein is a method and apparatus for injecting a fault and analyzing fault tolerance. The fault tolerance analysis apparatus extracts design information from a design. The fault tolerance analysis apparatus may inject a fault into a simulation of the design based on the extracted design information and parameters, and analyzes an influence of the fault on the simulation. Accordingly, in accordance with the fault tolerance analysis apparatus, fault tolerance for the fault injected into the simulation is analyzed, and the effect of the fault tolerance mechanism provided in the design is analyzed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.