Patent · US Active

Process for fabricating a transistor structure including a plugging step

US10490451B2 · kind B2 · utility

0Cited by

4References

19Claims

0Family size

Assignee

COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES · FR

Inventors

Laurent Brunet · Léguevin, FR
Nicolas Posseme · Grenoble, FR

Key dates

Filing date	Jun 16, 2017
Grant date	Nov 26, 2019
Priority date	—
Expiry date	Jun 16, 2037

Classification

Technology area (CPC H)Electricity
CPC primaryH10D88/00
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A process for fabricating a transistor structure produced sequentially, comprises at least one string of the following steps: producing at least one first transistor from a first semiconductor layer possibly made of silicon; encapsulating at least the first transistor with at least one first dielectric layer defining a first assembly; bonding a second dielectric layer located on the surface of a second semiconductor layer possibly made of silicon, to the first dielectric layer; depositing a planarizing material layer on the surface of the second semiconductor layer; selectively etching the planarizing material layer, to the second semiconductor layer; and producing at least one second transistor from the second semiconductor layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.