Inventor · Grenoble, FR

Nicolas Posseme

78Patents
4h-index
57Co-inventors
65Inventor score

Filing activity: Jun 9, 2011 → Oct 14, 2022

Most-cited inventions

PatentTitleAreaCited byStatus
US9570317B2 Microelectronic method for etching a layer Electricity 11 Active
US9257293B2 Methods of forming silicon nitride spacers Electricity 8 Active
US9378970B2 Plasma etching process Electricity 8 Active
US10043890B2 Method of forming spacers for a gate of a transistor Electricity 6 Active
US9054045B2 Method for isotropic etching Electricity 4 Active
US9583339B2 Method for forming spacers for a transistor gate Electricity 3 Active
US10062602B2 Method of etching a porous dielectric material Electricity 3 Active
US9543409B2 Production of spacers at flanks of a transistor gate Electricity 2 Active
US9853124B2 Method for fabricating a nanowire semiconductor transistor having an auto-aligned gate and spacers Electricity 2 Active
US9337350B2 Transistor with reduced parasitic capacitance and access resistance of the source and drain, and method of fabrication of the same Electricity 2 Active
US8956886B2 Embedded test structure for trimming process control Electricity 2 Active
US9607840B2 Method for forming spacers for a transistor gate Electricity 1 Active
US9437418B2 Method for forming spacers for a transistor gate Electricity 1 Active
US10347545B2 Method for producing on the same transistors substrate having different characteristics Electricity 1 Active
US9780191B2 Method of forming spacers for a gate of a transistor Electricity 1 Active
US9947768B2 Method for forming spacers for a transistor gate Electricity 1 Active
US10573529B2 Method of etching a three-dimensional dielectric layer Electricity 1 Active
US12087707B2 Method of making an individualization zone of an integrated circuit Electricity 1 Active
US10795257B2 Method for forming a functionalised guide pattern for a graphoepitaxy method Electricity 1 Active
US9780000B2 Method for forming spacers for a transitor gate Electricity 1 Active
US9947541B2 Method of forming spacers for a gate of a transistor Electricity 1 Active
US11127835B2 Method for etching a three-dimensional dielectric layer Electricity 1 Active
US9698250B2 Method for the surface etching of a three-dimensional structure Electricity 1 Active
US10446408B2 Process for etching a SiN-based layer Electricity 1 Active
US9076732B2 Method to prepare semi-conductor device comprising a selective etching of a silicium—germanium layer Electricity 1 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.