IC with larger and smaller width contacts
US10490547B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 3, 2018 |
| Grant date | Nov 26, 2019 |
| Priority date | — |
| Expiry date | Aug 3, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/813
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (IC) includes a substrate having a semiconductor surface layer, at least one capacitor above the semiconductor surface layer including a bottom plate, a capacitor dielectric over the bottom plate, and a top plate over the capacitor dielectric, functional circuitry in the semiconductor surface layer includes a core region having transistors configured together with the capacitor for realizing at least one circuit function. Electrically conductive metal filled contacts are through the dielectric layer that contact the top plate, the bottom plate, and the core region, including a first filled contact hole having a first depth and a first width that reach the top capacitor plate, and second filled contact hole having a second depth and a second width that reach the core region. The second depth is deeper than the first depth, and the first width is at least ten (10) % larger than the second width.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.