Larger-area integrated electrical metallization dielectric structures with stress-managed unit cells for more capable extreme environment semiconductor electronics

US10490550B1 · kind B1 · utility

Assignee

• United States of America as represented by the Administrator of NASA · US

Inventors

• David J. Spry · Medina, US
• Philip G. Neudeck · Berea, US

Key dates

• Filing date: Feb 21, 2017
• Grant date: Nov 26, 2019
• Expiry date: Feb 23, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D1/696

Abstract

A process of fabrication and the resulting microelectronic device that realizes metal features with larger lateral areas to maintain damage-free integrity over larger temperature ranges. The process and device enable the realization of highly durable extreme-environment microelectronic integrated circuits with increased functional capability, including realization of larger-area on-chip integrated metal-insulator-metal capacitor devices.