Method of forming metal silicide layer, semiconductor device and method of fabricating same
US10490647B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2018 |
| Grant date | Nov 26, 2019 |
| Priority date | — |
| Expiry date | Aug 31, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/663
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a metal silicide layer, a semiconductor device and a method for fabricating the device are disclosed. Through depositing a buffer layer between a metal layer and a substrate, metal atoms in the metal layer will diffuse, during a thermal annealing process, through the buffer layer into the substrate while being buffered by the buffer layer. As a result, the diffusion speed and depth of the metal atoms in the substrate are both reduced, and a reaction between the metal and silicon in the substrate is hence slowed down. In this way, the risk of agglomeration of the resulting metal silicide can be effectively lowered, avoiding pinhole defects occurring in the substrate and improving the interface roughness of the resulting metal silicide layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.