Power semiconductor device

US10490658B2 · kind B2 · utility

Assignee

• ABB Schweiz AG · CH

Inventors

• Lars Knoll · Cokeville Municipal Airport access, CH
• Renato Minamisawa · Windisch, CH

Key dates

• Filing date: Aug 2, 2018
• Grant date: Nov 26, 2019
• Expiry date: Aug 2, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/516

Abstract

A power semiconductor device includes a plurality of vertical field effect transistor cells arranged in a plurality of parallel rows, each row including vertical field effect transistor cells arranged along a first direction, wherein in each vertical field effect transistor cell a body region is surrounded by the gate layer from two lateral surfaces of the body region opposite to each other. In each row of vertical field effect transistor cells the body regions are separated from each other in the first direction by first gate regions of the gate layer, each first gate region penetrating through the body layer, so that in each row of vertical field effect transistor cells the first gate regions alternate with the body regions along the first direction. The first gate regions within each row of vertical field effect transistor cells are connected with each other by second gate regions extending across the body regions of the respective vertical field effect transistor cells in the first direction. The first gate regions and the second gate regions form continuous gate strips extending with its longitudinal axis in the first direction. A source electrode is formed on the source layer…