Flop circuit with integrated clock gating circuit
US10491197B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 20, 2017 |
| Grant date | Nov 26, 2019 |
| Priority date | — |
| Expiry date | Dec 6, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/35625
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An electronic circuit is disclosed. A first flip-flop is coupled to receive a clock signal from clock gating circuit. The first flip-flop includes an input circuit having a data input, a master-slave latch, and an output circuit. Responsive to an edge of the clock signal, the master-slave latch may latch a logic value of a signal received on the data input. The output circuit is coupled to the master-slave latch, and provides a logic output signal corresponding to the logic value latched by the master-slave latch. The clock gating circuit may provide one or more inversions of the clock signal which it receives. The flip-flop provides no inversions of the clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.