System architecture method and apparatus for adaptive hardware fault detection with hardware metrics subsystem
US10495691B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 9, 2018 |
| Grant date | Dec 3, 2019 |
| Priority date | — |
| Expiry date | Mar 17, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1208
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method, system, and architecture (100) for adaptively field testing for hardware faults on an integrated circuit device includes a central quality assurance server (121) which receives specified hardware metric data (131) monitored at an integrated circuit device (110) in the field, identifies prioritized built-in self-test (BIST) fault detection tests (134) based on the specified hardware metric data, securely downloads the prioritized BIST fault detection tests (132) to the integrated circuit device for execution to identify a first hardware fault at the integrated circuit device, and then receives diagnosis information (133) identifying the first hardware fault from the integrated circuit device which is used to update the prioritized BIST fault detection tests.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.