Parallel dispatching of multi-operation instructions in a multi-slice computer processor
US10496412B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 8, 2016 |
| Grant date | Dec 3, 2019 |
| Priority date | — |
| Expiry date | Aug 22, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/80
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Parallel dispatching of multi-operation instructions in a multi-slice computer processor, including: determining whether an instruction must be broken into a plurality of smaller operations; marking each of the smaller operations as instructions to be dispatched in parallel; determining whether each of the operations can be dispatched to distinct instruction issue queues during a same clock cycle; and responsive to determining that each of the operations can be dispatched to distinct instruction issue queues during the same clock cycle, dispatching each of the operations to distinct instruction issue queues during the same clock cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.