Inventor · Austin, TX, US

Kurt A. Feiste

42Patents
13h-index
53Co-inventors
84Inventor score

Filing activity: Dec 14, 1995 → Sep 1, 2021

Most-cited inventions

PatentTitleAreaCited byStatus
US6021485A Forwarding store instruction result to load instruction with reduced stall or flushing by effective/real data address bytes matching Physics 84 Expired
US8041928B2 Information handling system with real and virtual load/store instruction issue queue Physics 43 Active
US5926830A Data processing system and method for maintaining coherency between high and low level caches using inclusive states Emerging Cross-Sectional Technologies 38 Expired
US6349382B1 System for store forwarding assigning load and store instructions to groups and reorder queues to keep track of program order Physics 36 Expired
US5832276A Resolving processor and system bus address collision in a high-level cache Physics 27 Expired
US6134646A System and method for executing and completing store instructions Physics 23 Expired
US7350056B2 Method and apparatus for issuing instructions from an issue queue in an information handling system Physics 23 Expired
US5963978A High level (L2) cache and method for efficiently updating directory entries utilizing an n-position priority queue and priority indicators Physics 23 Expired
US6070238A Method and apparatus for detecting overlap condition between a storage instruction and previously executed storage reference instruction Physics 22 Expired
US5822765A System and method for resolving contention arising from execution of cache coherency operations in a multiple cache computer system Physics 21 Expired
US6658534B1 Mechanism to reduce instruction cache miss penalties and methods therefor Physics 17 Expired
US6266767A Apparatus and method for facilitating out-of-order execution of load instructions Physics 17 Expired
US5860100A Pipelined flushing of a high level cache and invalidation of lower level caches Physics 14 Expired
US11144319B1 Redistribution of architected states for a processor register file Physics 13 Active
US7412589B2 Method to detect a stalled instruction stream and serialize micro-operation execution Physics 13 Expired
US7437539B2 Issue unit for placing a processor into a gradual slow mode of operation in response to a detected livelock condition within a processor pipeline Physics 7 Active
US5974259A Data processing system and method of operation having input/output drivers with reduced power consumption and noise levels Emerging Cross-Sectional Technologies 6 Expired
US7434033B2 Placing a processor into a gradual slow mode of operation in response to a detected livelock condition within a processor pipeline Physics 4 Active
US8082423B2 Generating a flush vector from a first execution unit directly to every other execution unit of a plurality of execution units in order to block all register updates Physics 4 Active
US7818544B2 Processor livelock recovery by gradual stalling of instruction processing rate during detection of livelock condition Physics 3 Active
US8200946B2 Issue unit for placing a processor into a gradual slow mode of operation Physics 2 Active
US7949857B2 Method and system for determining multiple unused registers in a processor Physics 1 Active
US7953960B2 Method and apparatus for delaying a load miss flush until issuing the dependent instruction Physics 1 Expired
US10496412B2 Parallel dispatching of multi-operation instructions in a multi-slice computer processor Physics 1 Active
US7370176B2 System and method for high frequency stall design Physics 1 Expired

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.