Patent · US Active

Extracting selective information from on-die dynamic random access memory (DRAM) error correction code (ECC)

US10496473B2 · kind B2 · utility

11Cited by

14References

18Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Debaleena Das · Los Gatos, US
Bill Nale · Livermore, US
Kuljit S. Bains · DuPont, US
John B. Halbert · Beaverton, US

Key dates

Filing date	Oct 3, 2017
Grant date	Dec 3, 2019
Priority date	—
Expiry date	Jan 4, 2038

Classification

Technology area (CPC G)Physics
CPC primaryG06F11/1084
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Error correction in a memory subsystem includes a memory device generating internal check bits after performing internal error detection and correction, and providing the internal check bits to the memory controller. The memory device performs internal error detection to detect errors in read data in response to a read request from the memory controller. The memory device selectively performs internal error correction if an error is detected in the read data. The memory device generates check bits indicating an error vector for the read data after performing internal error detection and correction, and provides the check bits with the read data to the memory controller in response to the read request. The memory controller can apply the check bits for error correction external to the memory device.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.