Self-test capable integrated circuit apparatus and method of self-testing an integrated circuit
US10496506B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 17, 2017 |
| Grant date | Dec 3, 2019 |
| Priority date | — |
| Expiry date | Nov 17, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06596
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A self-test capable integrated circuit apparatus includes a pattern generator, a results store and testable logic. The testable logic includes a plurality of scan channels, each of the channels being respectively coupled between the pattern generator and the results store. A self-test controller is arranged to supervise a self-test in respect of the testable logic to generate self-test result data, the self-test result data being stored in the results store. A processing resource is coupled to the self-test controller and coupled between the pattern generator and the results store, the processing resource being capable of evaluating the self-test result data stored in the results store. The testable logic includes the processing resource, arranged to cooperate with the self-test controller. The processing resource is able, subsequent to the self-test, to evaluate the self-test result data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.