Memory device and method of operating same
US10497407B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 2018 |
| Grant date | Dec 3, 2019 |
| Priority date | — |
| Expiry date | Nov 30, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes: first and second terminal switches connected correspondingly between the first and second terminals of a sense amplifier and corresponding first and second nodes; first and second recycle switches connected correspondingly between the first and second nodes and corresponding third and fourth nodes; and first and second capacitors connected correspondingly between the third and fourth nodes; and wherein the first and second recycle switches are configured to selectively connect the first and second capacitors correspondingly to the first and second nodes in phases including as follows: during a recovery phase in which first and second gleaned amounts of charge (first and second gleaned charges) are recovered from corresponding selected ones of bit lines; and during a reuse phase in which the first and second gleaned charges are reused from correspondingly onto selected corresponding ones of the array of bit lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.