Hung-Chang Yu
61Patents
9h-index
19Co-inventors
75Inventor score
Filing activity: Dec 31, 1998 → Jan 2, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9165629B2 | Method and apparatus for MRAM sense reference trimming | Physics | 52 | Active |
| US8687412B2 | Reference cell configuration for sensing resistance states of MRAM bit cells | Physics | 31 | Active |
| US6366071B1 | Low voltage supply bandgap reference circuit using PTAT and PTVBE current source | Physics | 24 | Expired |
| US8493776B1 | MRAM with current-based self-referenced read operations | Physics | 16 | Active |
| US8902641B2 | Adjusting reference resistances in determining MRAM resistance states | Physics | 15 | Active |
| US6127853A | High speed current-mode sense-amplifier | Physics | 14 | Expired |
| US8509003B2 | Read architecture for MRAM | Physics | 14 | Active |
| US8923040B2 | Accommodating balance of bit line and source line resistances in magnetoresistive random access memory | Physics | 11 | Active |
| US8817553B2 | Charge pump control scheme using frequency modulation for memory word line | Physics | 9 | Active |
| US7710182B2 | Reliable level shifter of ultra-high voltage device used in low power application | Electricity | 9 | Active |
| US8964458B2 | Differential MRAM structure with relatively reversed magnetic tunnel junction elements enabling writing using same polarity current | Physics | 8 | Active |
| US9406367B2 | Method and apparatus for MRAM sense reference trimming | Physics | 7 | Active |
| US9110829B2 | MRAM smart bit write algorithm with error correction parity bits | Physics | 6 | Active |
| US9875774B1 | Memory device and method of operating same | Physics | 3 | Active |
| US6717208B2 | Disabling flash memory to protect memory contents | Electricity | 3 | Expired |
| US10147469B2 | Memory device and method of operating same | Physics | 2 | Active |
| US10998024B2 | Method for enhancing tunnel magnetoresistance in memory device | Physics | 2 | Active |
| US10497407B2 | Memory device and method of operating same | Physics | 2 | Active |
| US8654589B2 | Charge pump control scheme for memory word line | Physics | 2 | Active |
| US7062738B1 | Flash memory compiler with flexible configurations | Physics | 2 | Expired |
| US9747159B2 | MRAM smart bit write algorithm with error correction parity bits | Physics | 2 | Active |
| US8570792B2 | Magnetoresistive random access memory | Electricity | 2 | Active |
| US8369180B2 | Memory word line boost using thin dielectric capacitor | Physics | 2 | Active |
| US9299677B2 | Package with multiple plane I/O structure | Electricity | 1 | Active |
| US8842489B2 | Fast-switching word line driver | Physics | 1 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.