Manufacturing method of interconnect structure
US10497607B2 · kind B2 · utility
1Cited by
6References
20Claims
0Family size
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Key dates
| Filing date | Sep 21, 2017 |
| Grant date | Dec 3, 2019 |
| Priority date | — |
| Expiry date | Sep 22, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76856
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A manufacturing method of an interconnect structure including the following steps is provided. A dielectric layer is formed on a silicon layer, wherein an opening exposing the silicon layer is in the dielectric layer. A metal layer is formed on the surface of the opening. A stress adjustment layer is formed on the metal layer. A thermal process is performed to react the metal layer with the silicon layer to form a metal silicide layer on the silicon layer. The stress adjustment layer is removed after the thermal process is performed. A barrier layer is formed on the surface of the opening.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.