High density wafer level test module
US10497630B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 5, 2018 |
| Grant date | Dec 3, 2019 |
| Priority date | — |
| Expiry date | Apr 5, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/47
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electronic device, e.g. an integrated circuit, includes one or more test modules each having first and second pairs of contact pads arranged along a first axis, and a third pair of contact pads arranged along a second axis parallel to the first axis. A first connection bus connects contact pads in the first pair, a second connection bus connects contact pads in the second pair, and a third connection bus connects contact pads of the third pair. A first device under test (DUT) is connected between the first connection bus and the third connection bus, and a second DUT is connected between the second connection bus and the third connection bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.