Hybrid die stacking
US10497669B2 · kind B2 · utility
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19Claims
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Assignee
Inventors
Key dates
| Filing date | Dec 21, 2016 |
| Grant date | Dec 3, 2019 |
| Priority date | — |
| Expiry date | Aug 8, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06589
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a die stack. The die stack may include a first plurality of dies and a second plurality of dies. Each of the plurality of dies may define a plurality of vias passing from a first side to a second side of the die. The plurality of dies may be stacked such that each of the plurality of vias in a first die are collinear with a respective via in a second die. At least one of the second plurality of dies may be wire bonded to at least one of the first plurality of dies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.