Metal-oxide semiconductor (MOS) standard cells employing electrically coupled source regions and supply rails to relax source-drain tip-to-tip spacing between adjacent MOS standard cells
US10497702B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 14, 2017 |
| Grant date | Dec 3, 2019 |
| Priority date | — |
| Expiry date | Aug 29, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/981
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Metal-oxide semiconductor (MOS) standard cells employing electrically coupled source regions and supply rails to relax source-drain tip-to-tip spacing between adjacent MOS standard cells are disclosed. In one aspect, a MOS standard cell includes supply rails disposed in a first metal layer and along respective axes in an X-axis direction. The MOS standard cell includes metal lines disposed in the first metal layer and along respective axes in the X-axis direction. The MOS standard cell includes a source region formed in a semiconductor substrate beneath the first metal layer and adjacent to a plane in an X-Z-axis direction disposed between a supply rail and the source region. The source region is electrically coupled to the corresponding supply rail. Forming the source region in this manner allows the MOS standard cell to be disposed adjacent to other MOS standard cells while achieving the minimum required source-drain tip-to-tip spacing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.