Glitch immune cascaded integrator comb architecture for higher order signal interpolation
US10498312B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 17, 2017 |
| Grant date | Dec 3, 2019 |
| Priority date | — |
| Expiry date | Dec 9, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H17/0671
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital filtering method includes receiving a digital signal, and passing the digital signal through a Pth order comb cascade. The method includes beginning pre-computing of intermediate integrator states of a Pth order integrator cascade as a function of the digital signal, prior to receiving output from a last comb of the Pth order comb cascade. The outputs from each comb of the Pth order comb cascade are then applied to the pre-computed intermediate integrator states to thereby produce a filtered version of the digital signal. The Pth order comb cascade may operate at a sampling frequency, and the pre-computing of the intermediate integrator states is performed at the sampling frequency, while the application of the outputs from each comb of the Pth order comb cascade to the pre-computed intermediate integrator states is performed at a multiple of the sampling frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.