Scalable low-latency storage interface
US10503434B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 12, 2017 |
| Grant date | Dec 10, 2019 |
| Priority date | — |
| Expiry date | Nov 24, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods are disclosed, including a host interface circuit configured to control communication between a set of virtual functions (VFs) and a media management system (MMS). The host interface circuit can consolidate commands from the set of VFs, dynamically allocate write buffers (WBs) from a set of available WBs to the set of VFs using the commands, and manage WB access for the set of VFs and provide write data to the MMS using the allocated WBs. For each VF in the set of VFs, the host interface circuit can manage a submission queue (SQ) for a respective VF from the set of VFs, receive a command from the respective VF, including one or more submission queue entries (SQEs), and coordinate the one or more received SQEs with allocated WBs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.