Dynamic per-bank and all-bank refresh
US10503670B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2017 |
| Grant date | Dec 10, 2019 |
| Priority date | — |
| Expiry date | Mar 1, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/40603
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, apparatuses, and methods for performing efficient memory accesses in a computing system are disclosed. In various embodiments, a computing system includes computing resources and a memory controller coupled to a memory device. The memory controller determines a memory request targets a given rank of multiple ranks. The memory controller determines a predicted latency for the given rank as an amount of time the pending queue in the memory controller for storing outstanding memory requests does not store any memory requests targeting the given rank. The memory controller determines the total bank latency as an amount of time for refreshing a number of banks which have not yet been refreshed in the given rank with per-bank refresh operations. If there are no pending requests targeting the given rank, each of the predicted latency and the total bank latency is used to select between per-bank and all-bank refresh operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.